This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to the formation of capacitor plates in memory devices such as ferroelectric memories.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits.
Non-volatile solid-state read/write random access memory (RAM) devices based on ferroelectric capacitors, such memory devices commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, have been implemented in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T2C (two transistor, two capacitor) cells. Another type of FRAM cell is based on the well-known “6T” CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.
As mentioned above, polarizability of the ferroelectric material provides the mechanism for non-volatile storage of a binary state in a ferroelectric capacitor. FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance that a ferroelectric capacitor exhibits between its polarized states. In the operation of a typical FRAM, the logic state stored by a memory cell is read by interrogating the capacitance, and thus the polarized state, of its ferroelectric capacitor. Referring to the example of FIG. 1, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), by way of which polarization charge involved in the change of polarization state is retained within the capacitor as the voltage exceeds its coercive voltage Vα; on the other hand, a capacitor already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned prior to the application of the voltage. The polarization ability of a ferroelectric capacitor is reflected in the difference in polarization charge between its “−1” and “+1” polarization states (i.e., (+Q1−(−Q2)), which is commonly referred to as the switching polarization parameter Psw. A relatively large value of switching polarization Psw means will be reflected in a large value of capacitance C(−1) relative to the value of capacitance C(+1). On the other hand, if switching polarization Psw is relatively low (and assuming that coercive voltages +Vα and −Vβ remain constant), the capacitance line C(−1) will have a flatter slope, reflecting a lower capacitance. The difference in capacitances between the two polarization states of the capacitor thus reduces as switching polarization parameter Psw decreases, which appears as a poorer read margin for the corresponding FRAM cell. Conversely, a higher value for switching polarization parameter Psw corresponds to an improved read margin for the FRAM cell.
It has been observed that the parameter of switching polarization Psw depends strongly on the manner in which the ferroelectric capacitor dielectric material is formed, particularly for the case of lead-zirconium-titanate (PZT). As described in U.S. Pat. No. 6,730,354, incorporated herein by reference, the formation of a PZT film in the manufacture of a semiconductor integrated circuit is commonly carried out by way of metalorganic chemical vapor deposition (MOCVD). It has been observed that this MOCVD technique is capable of depositing a very thin PZT film of sufficient quality to serve as a capacitor dielectric. More specifically, it has been observed that the MOCVD conditions of low precursor flow (the collective flow rate of the lead, zirconium, and titanium precursors, and the appropriate solvent of less than about 1.1 ml/min) and a process temperature below about 640 deg C. can provide a thin PZT film that, as the dielectric of a ferroelectric capacitor, can exhibit a relatively high switching polarization Psw.
However, it has also been observed that the low flow rate, low temperature, MOCVD deposition of PZT necessarily results in a very low deposition rate and a corresponding high consumption of the precursors. The resulting low manufacturing throughput and high material costs increase the manufacturing cost of the FRAM devices. The deposition rate of MOCVD PZT at this low temperature cannot be increased by increasing the precursor flow rate, because of the inability to closely control the relative nucleation of lead, zirconium, and titanium at such higher flow rates under low temperature. In particular, it has been observed that the relative nucleation of lead and lead oxide tends to increase under low temperature, absent close control of the individual precursor flows. The increased nucleation of lead forms an undesired second phase with a rough spatial morphology, appearing as a “haze” in the deposited film when viewed using light-scattering techniques. This roughness of the “haze” defects is also reflected in degraded electrical performance of the ferroelectric elements, typically as increased leakage, and thus reduced electrical yield and poorer device performance.